CSx35: Computer Architecture
| Semester: second | Year: third | Duration of Final Exam: 3 hours |
| Lecture Hours/Wk: 4 | Tutorial Hours/Wk: 1 | Lab Hours/Wk: 0 |
Marks:
| Semester work: 50 | Final: 75 | Total: 125 |
Instructor:
Dr Ahmed El-Mahdy
Computer Dep. 2nd floor Admin. Bldg
Course Scope
This is a first module in computer architecture. It aims to give the students a solid understanding of computer hardware; that involves examining what is inside a computer and how it operates. The modules also aims to teach students the skill of designing computer hardware as complex as a full processor design. Understanding how computer works in full details is also useful for designing high performance computer programs. Thus the module is targeting both software and hardware oriented students.
Objectives
After finishing this course, the student should be able to:
- Understand how a program written in a high-level language executes on the computer
- Determine the performance of a program and how the programmer could make it run faster
- Understand how the hardware alone can speedup the execution of programs
Course Outline
- Computer and abstraction and technology (1 week)
- Instruction set design (2 weeks)
- Computer Arithmetic (1 week)
- Introduction to performance evaluation (1 week)
- Serial processor design (2 weeks)
- Pipelined processor design (2 weeks)
- Memory hierarchy design (2 weeks)
- Input/Output design (time permits)
- Multiprocessors and clusters (time permits)
Examinations
There are two main exams: mid-term and final exams.
There are also various tutorial and lab assignment with details later on in sha Allah.
Lectures Log
Lab Schedule
| Week No. | Lab Contents | Assignment |
|---|
| 4 | Design of 32-bit register, multiplexers, comparators, adders.
Solving problems 2.5, 2.15, 2.29 | Download |
| 6 | Design of 32-register register file, memory module | Download |
| 8 | Design of 32-bit ALU with preliminary operations | Download |
| 10 | Design of a single cycle processor control unit |
| 12 | Integrating previously designed modules into a single cycle MIPS |
| 14 | Upgrading to a multicycle MIPS (time permits) |
| 16 | Upgrading to a pipelined MIPS (time permits) |
- All designs are to be in pure VHDL.
- Further detailed lab contents shall be given prior to each lab session.
Course Work
TBA (To Be Arranged) in sha Allah
Grading Policy
| Mid term exam | 20% |
| Lab assginments | 15% |
| Tutorial assignments | 5% |
| Final exam: | 60% |
| Total: | 100% |
Textbook
- David A. Patterson and John L. Hennessy, Computer Organization and Design: The Hardware / Software Interface, Elsevier-Morgan Kaufmann, 2005.
Internet Resources
